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Si4730/31-D50
Table 4. Reset Timing Characteristics 1,2,3
(V A = 2.7 to 5.5 V, V D = 1.62 to 3.6 V, T A = –20 to 85 °C)
Parameter
RST Pulse Width and GPO1, GPO2/INT Setup to RST ? ?
GPO1, GPO2/INT Hold from RST ?
Symbol
t SRST
t HRST
Min
100
30
Typ
—
—
Max
—
—
Unit
μs
ns
Important Notes:
1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the first start condition.
3. When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
4. If GPO1 and GPO2 are actively driven by the user, then minimum t SRST is only 30 ns. If GPO1 or GPO2 is hi-Z, then
minimum t SRST is 100 μs, to provide time for on-chip 1 M ? devices (active while RST is low) to pull GPO1 high and
GPO2 low.
t SRST
t HRST
RST
GPO1
GPO2/
INT
70%
30%
70%
30%
70%
30%
Figure 1. Reset Timing Parameters for Busmode Select
6
Rev. 1.0